A computer system may include various types of computer memory. For example, the computer memory may include random access memory (RAM) that is used for primary storage in a computer system. The computer system may also include read-only memory, flash memory, magnetic computer storage devices, etc.
The computer memory may be non-uniform in that different tiers of the computer memory may include different values for qualities including latency, throughput, endurance, and capacity. Latency may be described as a delay before a transfer of data or execution of a command begins following an associated instruction for transfer of the data or execution of the command. Throughput may be described as a rate at which data may be read from or stored into the computer memory. Further, endurance may be described as the number of program and/or erase cycles that may be applied to the computer memory before the computer memory becomes unreliable. Capacity may be described as a size of storage available to store content.
In order to optimize the computer system performance, content in the computer memory may need to be moved, for example, for re-allocation of the computer memory. For example, content in the computer memory may need to be placed in an appropriate tier of the computer memory. In this regard, there may be situations where the content is to be moved from one physical location to another, without stopping or otherwise delaying the possible users of the computer memory. For example, for an hypervisor in a non-uniform memory system, a specified portion of the computer memory may need to be relocated between different physical locations. In this regard, it is technically challenging to relocate the specified portion of the computer memory without any interruption with respect to usage of the specified portion of the computer memory. For example, usage of the specified portion of the computer memory may include direct memory access from peripheral devices such as a network or a solid-state drive (SSD), and a hypervisor may not be aware of how or when the direct memory access may be scheduled. In this regard, it is technically challenging to move memory blocks in such a way that the memory block user perceives no interruption or error.